can I adopt clock enable?

[lightcloud]

In my design, clocks of submodule have frequnce divided by main clock,
If I use divided clock,the generated clock has delay cause by d flip-flop,
and I should create many clokc in synthesis and do clock tree for every
clock,and the scan_chain sheme is complicated,So could I use clock enable
signal for main clock,and this could decrease the complicity of the backend
work.

 

[yln2k2]

Hi ,

1) You need to create generated clk for each divider . And I think you need to do clk tree for create clk , not to generated clk .
If you use any CTS engine it will take care .
2) Regarding Scan methodology , if you use scan clk separate ( not at speed scan) then try to add spike free mux after generate clk which has one I/P as scan clk .
ask CTS to balance from o/p of spike free mux .
with this you don't need to do clk balance separately ...

If you don't want to do any of the above still you want to achieve devide clk using clk_enable . please make sure following .
1) You need to balance clk_enable with main clk to avoid glitches in clk path ?
2) what type of divisions you are looking at ? some thumb rules are if you are doing devide by 2 then shift enable half cylce so that it clk puluse is gaurnteed ....



Thanks & Regards
yln

 

[jackson_peng]

Well, u're worry about the complicated clock tree, which is separated by the clock divider logic.

however, to keep the clock tree as a unit, you can apply gating style clock divider.

regards