Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Can function be used in Verilog RTL?

Status
Not open for further replies.

lostin_eda

Newbie level 6
Joined
Aug 16, 2007
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,366
could function be used in Verilog RTL?
 

guzhal

Junior Member level 3
Joined
Feb 24, 2007
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,469
Re: function used in RTL

Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit. In VHDL functions can be used, as there is concept of subprograms which comprises of procedures and functions .
I am not sure about verilog
 

lostin_eda

Newbie level 6
Joined
Aug 16, 2007
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,366
Re: function used in RTL

guzhal said:
Register transfer level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit. In VHDL functions can be used, as there is concept of subprograms which comprises of procedures and functions .
I am not sure about verilog

Sometimes, ALWAYS could be used in stead of FUNCTION. This kind use of FUNCTION could be used in RTL?
 

guzhal

Junior Member level 3
Joined
Feb 24, 2007
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,469
Re: function used in RTL

always is a function used in verilog not in VHDL
 

heartfree

Advanced Member level 4
Joined
Oct 31, 2004
Messages
100
Helped
3
Reputation
8
Reaction score
2
Trophy points
1,298
Activity points
738
function used in RTL

Yes, Function feature can be used in verilog as a combination logic implementation.
 

optor

Member level 3
Joined
Nov 25, 2003
Messages
62
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
350
Re: function used in RTL

lostin_eda said:
could function be used in Verilog RTL?

Sure, but it is suggested that using function only in testbench.
 

supercst

Member level 2
Joined
Mar 21, 2004
Messages
44
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
289
Re: function used in RTL

optor said:
lostin_eda said:
could function be used in Verilog RTL?

Sure, but it is suggested that using function only in testbench.

maybe not suggested. only task can only be used in testbench. sometimes function will be convenient for some circuits.

almost all the systhesis tools support functions.
 

beta0

Member level 5
Joined
Nov 24, 2003
Messages
88
Helped
7
Reputation
14
Reaction score
2
Trophy points
1,288
Activity points
393
Re: function used in RTL

heartfree said:
Yes, Function feature can be used in verilog as a combination logic implementation.

Right, Function are usually used for implementation some combination logic at RTL
level
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top