CAN controller in XILINX FPGA

[kaustubhkhole]

My project is to implement CAN controller in XILINX FPGA using VERILOG HDL.....

The problem I am facing is that, when two devices write a xero and one at the same time instant I get an x on the bus ...........this is an unsyntnesizable code.........

One of the approach is to add a controller ther ..........but it kills the HOT-Swappabality and the purpose of the CAN to minimize wires and thus the complexity !!!!


Can any one suggest something else ????

Waiting for your valuable replies !!!!

 

[EDALIST]

Your Project Is To Make A CAN Controller.

You Will Need A CAN Transceiver To Connect To CAN Bus.

 

[kaustubhkhole]

Exactly......I don't have any transciever...I have to program it from scratch !!!!

That's where I am facing a problem !!!!

Can you suggest me any ARCHITECTURE ??

 

[EDALIST]

My Point Is That You Are Not Suppose To Design The Transceiver, You Can Buy It From Companies Like TI.
What You Need To Do Is To Design Just The Controller And Emulate The Transceiver.