i want a 4*clk and a 16*clk.clk in the input clock.would u explain more ? thanks
You should know the input clock rate from your project specifications.
Whether you do it for 256x256 or larger video the principal (and probably the logic) is all the same. Just the clocks are faster.
The clock you're interested in is the pixel clock - for your 256x256 video the pixel clock is 16.4 Mhz (assuming no blanking)
Video in FPGA is quite straight forward. Why did you think you need 4x and 16x clocks?
thanks ,will u explain it more?I think you should be running everything at the 26.2144 MHz (16x clock) and just generate enables at the lower rates. But that is part of the system design architecture, which despite the drawing in the other post doesn't appear to be well defined.
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