CAN ANYONE PLS FIGURE OUT D PROB..(VERILOG MODELLING STYLE)

[naizath12]

verilog2001 and conditional generate

i composed the following program.


module division_try(/*divisor,dividend,*/quotient,remainder);
output [3] quotient;
output [3] remainder;
//input [3] divisor;
//input [3] dividend;

reg [3] divisor='b10; //initialise
reg [3] dividend='b1010; //initalise


reg [3] divisor_alias;
initial
divisor_alias=divisor;

reg [3] quotient;
initial
quotient=dividend;


reg aMSB_old;
reg [3] remainder;
reg[7] concat_aq;
integer n;


always
begin

for(n=0;n<4;n=n+1)
begin
concat_aq={remainder,quotient};
concat_aq=concat_aq<<1;

if(aMSB_old)
begin
adder4 ////ERROR HERE////////////////////////
A1(remainder,divisor_alias,'b0,remainder);
end

else if(aMSB_old==0)
begin
sub4 /////ERROR HERE////////////////////////
A2(remainder,divisor_alias,'b0,remainder);
end

aMSB_old=remainder[3];

case (aMSB_old)
1: quotient[0] = 0;
0: quotient[0] = 1;
endcase
end

if(aMSB_old)
begin
adder4 //////ERRORHERE////////////////////////
A3(remainder,divisor,'b0,remainder);
end

end
endmodule


and when i synthesized the code(the modules for adder4 and sub4 which they themselves call another another submodule each)
I wasnt able to synthesize

i got the following error message

ERROR:HDLCompilers:26 - "division.v" line 57 unexpected token: 'adder4'
ERROR:HDLCompilers:26 - "division.v" line 63 unexpected token: 'sub4'
ERROR:HDLCompilers:26 - "division.v" line 77 unexpected token: 'adder4'

have i gone wrong in the flow??.....are v not supposed to use continuous statements inside a procedural block??....(in my case i have tried using assign-deassign & force-releasse also but in vain....

can u ppl help me??...

Added after 4 hours 1 minutes:

ppl the problem is with the flow....
i have instantiated a module within an always statement!!!!!

but i want to call my modules(adder4 and sub4) in a sequential manner....
how do i do this?

thnx in advance

 

[vlsi_whiz]

error:hdlcompilers:26

I think you're trying to do a conditional generation logic... This cannot be done using the simple If-else.. What you need to do is use the If-generate statements, ie, conditional generate...

generate
if
else
endgenerate

 

[naizath12]

task inside generate statement in verilog

i tried using tat too...but in vain....
i also tried using assign-deasign statements & also force-release(4 simulation purpose alone) too...but didnt work....

as of wat i heard frm a verilog expert.. he says tat i cannot use module instantiation inside an always statemnt....

but i do not know how to execute a code which using different modules in a sequential manner.....

 

[oursriharsha]

remainder verilog function code

they will be called sequentially automatically when used with if statement .
instantiate them

 

[naizath12]

verilog divisor

you mean..


if(condition)
begin
module 1;
elseif (condition)
module 2
else
module3
end

...i tried tis...it doesnt work..'coz an if-else needs an
always statement!!!!!!....else u get an error like
ERROR:HDLCompilers:26 - "division.v" line 51 expecting 'endmodule', found 'if'

....

 

[sheik_vb]

verilog error unexpected token:

Hi,

In the below instantiation, can u change 'b0 to 1'b0 and try......

A1(remainder,divisor_alias,'b0,remainder);

 

[shashank.nag]

verilog error unexpected token in case

Hi naizath

Can you visualize what you are actually trying to do by conditionally instantiating the adders / subtractors in this code.

In general. conditional instantiation in possible in Verilog2001 but as mentioned earlier using the generate construct. but that is not what your intention here should be.

You are trying to use the general programming concept of calling the required function depending on the input you have received. The case is not the same in HDL. Here instantiations (even if conditional) can depend only on values that do not change runtime. Thus instantiations should depend only on values like `define or parameters or constants...

You should understand the fact that the resulting hardware cannot have any way of generating the required adder / subtractor on its own. You have to instantiate them to use them.

 

[naizath12]

verilog conditional generation

thnx ppl.......
i have resolved the problem...
instead of instantiating modules i shud've used task/function(its jest a routine call)....
now its working phaka!!!!!