Can anyone help to intepret this verilog expression?

[zhiling0229]

Hi,

I'm a noob in verilog language, I was looking through a verilog code an encounter this expression:

parameter DATA_WIDTH = 72

reg [DATA_WIDTH - 1: 0] data;
reg [DATA_WIDTH - 1: 0] ndata;

wire [1:0] data_background

data <= { (DATA_WIDTH + 1) / 2 {data_background}};
ndata <= { (DATA_WIDTH + 1) / 2{~data_background}};

The signal that is going into data_background is 2 b'11

Can anyone help me explain how the not is performed for ~data_background and what does the curly braces means for this case?

Can anyone help me to provide me with the expected output of data and ndata?


Thanks a million

 

[FvM]

That's basic verilog syntax, a concatenation with a repeat factor. In this case, all one is copied to both regs.

You should take the time to learn basic Verilog syntax from a text book to get full benefit from the language.

 

[zhiling0229]

Thanks for the answer.

Your right I need to have to learn more on the verilog basic syntax. Any books that you can recommend to learn the verilog basic syntax?

Hmmm......was wondering:

Why both ndata and data be the same values when one is concatenated with:

data_background and the other is ~data background?

In this case will data_background and ~data_background have the same value? when will it have a different value?

 

[j_andr]

/.../Any books that you can recommend/.../

you can try google and a string: verilog examples OR tutorial;

"~" means not, an inverter;
---

 

[FvM]

You are right, I overlooked the inversion.