Can anyone checking my work about FSM/VHDL

[saifaljanahi]

Hello all, I want to show you the FSM diagram that implements the block diagram shown below, this is my effort to the course project, I have the code if anyone want to check it.

 

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The problem description doesn't seem to match what you drew as your FSM.

There isn't anything mentioned in the text for transitioning from the 2nd state to the Reset state. Also there are two transitions from the 3rd state back to the first state. You also don't have any transition that loops in both the 2nd and 3rd states to account for the "receive the done signal" and the "all number has been read and displayed" respectively.

 

[saifaljanahi]

The problem description doesn't seem to match what you drew as your FSM.

There isn't anything mentioned in the text for transitioning from the 2nd state to the Reset state. Also, there are two transitions from the 3rd state back to the first state. You also don't have any transition that loops in both the 2nd and 3rd states to account for the "receive the done signal" and the "all number has been read and displayed" respectively.

Thanks,
so what you suggest modifying this FSM as the text and the block diagram?
I think the reset state is the same as the ideal state and as my instructor said.

 

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ideal state? I think you mean an idle state.

Yes you need to follow what the design requirements are, which is the problem description your instructor gave you. Right now the FSM sequence of states doesn't do anything close to what the sequence describe by the problem text.

The block diagram shows you what the instructor wants your signal names to be that go between FSM and the other blocks.

Also I didn't look at the block diagram all that closely, so didn't realize you were cycling in state Reset with Key0, Key0 should be a FSM reset signal forcing the FSM to the IDLE state.

Also you need to debounce and synchronize any switch input like these Key0/1 inputs to the FSM clock.

 

[saifaljanahi]

ideal state? I think you mean an idle state.

Yes you need to follow what the design requirements are, which is the problem description your instructor gave you. Right now the FSM sequence of states doesn't do anything close to what the sequence describe by the problem text.

The block diagram shows you what the instructor wants your signal names to be that go between FSM and the other blocks.

Also I didn't look at the block diagram all that closely, so didn't realize you were cycling in state Reset with Key0, Key0 should be a FSM reset signal forcing the FSM to the IDLE state.

Also you need to debounce and synchronize any switch input like these Key0/1 inputs to the FSM clock.

Thanks, I've modified it according to your recommendation and according to the text.

Please can you check it again? is this FSM right?

 

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I know this seems like I'm being nitpicky, but first of all the state name "ideal" is a poor state name as it implies by the words definition a "perfect" state, see ideal definition. What you want to call the state is IDLE which implies that state is for sitting around waiting for something to do. To different words with entirely different meanings.

Key(0) is the reset, it should not be a state transition control for the "IDLE" state. It should be a reset to the FSM state register. It is not included as part of the FSM's case statements.

Key(1) has only one exit (when active) from the "IDLE" state, what is supposed to happen if Key(1) is inactive? You've already correctly handled the exit conditions from the other two states, so it should be easy to see what you need to change to correct the "IDLE" state.

The other two states seem to match what is described in the problem text.