Can anyone checking my work about BCD/Verilog

[_Stavros_]

I'm a verilog beginner, I'm try to write a 24(29)-bit hexadecimal BCD counter. Can anyone explain how to implement it ?
Thanks !
Her is my code, but I'm need to check.
Who can help me ?


``

Code:

module binary_to_BCD(output [31:0] bcd,
        input [23:0]bin,
        input clk);
reg [31:0] bcd;
reg [4:0] i;
always@(posedge clk or bin)
begin
    bcd=0;
    for(i =0; i<24; i = i + 1)
    begin
        bcd = {bcd [30:0],bin[23-i]};
        if(i<23 && bcd[3:0] > 4)
            bcd[3:0] = bcd[3:0] + 3;
        if(i<23 && bcd[7:4] > 4)
            bcd[7:4] = bcd[7:4] + 3;
        if(i<23 && bcd[11:8] > 4)
            bcd[11:8] = bcd[11:8]+3;
        if(i<23 && bcd[15:12] > 4)
            bcd[15:12] = bcd[15:12] + 3;
        if(i<23 && bcd[19:16] > 4)
            bcd[19:16] = bcd[19:16] + 3;
        if(i<23 && bcd[23:20] > 4)
            bcd[23:20] = bcd[23:20] + 3;
        if(i<23 && bcd[27:24] > 4)
            bcd[27:24] = bcd[27:24] + 3;
        if(i<23 && bcd[31:28] > 4)
            bcd[31:28] = bcd[31:28] + 3;
    end
end
endmodule

 

[wwfeldman]

how did you test it?
what did you get when you tested it?

 

[vGoodtimes]

for this use-case, "double-dabble" is a better choice. but for a counting case you can optimize further. the trick there is to maintain the count in bcd on each cycle. the bcd to bcd+1 conversion is not as optimized as binary to binary+1, but the binary to bcd conversion scales worse.

 

[ads-ee]

always@(posedge clk or bin)

This isn't valid for synthesis, changing the value of "bin" in the middle of a clock cycle will cause the code to misbehave and the synthesis tools won't be able to implement such a circuit (unless it just ignores the "bin" in the sensitivity list)

You are also using blocking assignments (=) instead of non-blocking (<=) in a edge triggered always block. The basic rule is use non-block for flip-flops (i.e. when you use always @(posedge clk)) and blocking assignments for combinational code (i.e. when you use always @(*)).

Also the for loop isn't going to work like I think you expect. For loops in Verilog are spatially unrolled (makes 24 copies of the code you have between the begin-end). You seem to expect the for loop to behave like software where for loops are temporally unrolled (done sequentially in time).

In hardware if you want to count out time you create a counter and count out the time based on your clock period.

 

[vGoodtimes]

oh wait, this is double dabble. for some reason I thought those were else ifs. I'm dumb. it is intended to be unrolled this number of times. (although it can be serialized too). the amount of logic per iteration isn't terrible as everything is small sized. The resulting circuit is I think fairly decent for 1 cycle 24b binary to 8 bcd digit conversion.

in anycase, for a bcd counter student assignment they really want something like a bcd increment with carryout in some chain. that is a better way to do it.