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You don't have the engineer sense. Engineers are here to solve problem, and enjoy this (normaly , so doing some simple stuff like this, it is a pleasure. Poor USA if you have this kind of engineer.
1) draw a block diagram of the proposed circuit; label it with your ports
2) draw your timing waveforms; clock, reset, load, data-in, data-out
3) are you using Verilog RTL?
you could pull down my VIEW generator TCL script; this script generates a verilog module stub with a verilog testbench with clocks and resets defined. all you need to supply it are port names/types.
https://sites.google.com/site/jpvas...ect the necessary stimulus
6) design away...
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, so doing some simple stuff like this, it is a pleasure. Poor USA if you have this kind of engineer.
