can anybody explain this to me?

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tommydidi

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Hi guys,

I am not very sure about the operation of the following circuit. This latch and track circuit is a part of my comparator circuit. I1 and I2 come from the upper current mirror. The node X is connected to the next gain stage. Can anybody tell me how it works?
 

this circuit is often used in hysteresis comparator ,and it is used as a
positive feedback 。refer to allen
 

also can find detail explaination in jacob backer's cmos design layout and simulation book.
 

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