Can any one tell me the verfication of Design. and lang

[narasimhalu]

hi all
i am doing my M.tech project in singapore .now i am learning the vcs..
i am verify the design with vhdl test bench.now i want to learn full verification of the design.that's is like in companys..pls tell me what are the language used
for verification..and how it is useful than the testbench writing....
how can i learn verification in full...
thanks in advance
with regards
R.Narasimhalu

 

[gogogo]

verilog systemc etc, and u can use them.

 

[trilogy]

Verification of circuits is a hot property in EDA . Wll their are various tools available for verification by giats like Mentorgraphics, Synopsys. Wll i dont understand what u mean by language for verification.
Verification involves various methodologis like CTL, model checking etc.

 

[narasimhalu]

thanks for reply...
can u tell me what are the methods for verifications and explain it or give some notes about that..i mean lang like vera,specman

 

[trilogy]

first tell me whether your project involves developing some new methodology for verification or you just require tto use verification for some purpose in your project. As for latter case getting verse with any standard verification tool will be enough, else u need to know the various ways of verifcation .

 

[narasimhalu]

my project is Design only.i want to do some standard verfication, so that only i asked.right now i am using VCS for my project... and i also interested to learn more about the verification of the design ..
can you pls tell me

thanks in advance
with regards
R.Narasimhalu

 

[trilogy]

If u want to learm about verification through a tool , I think VCS is good enough. But if u want to learn about how verification actually is done, u have to look for MODEL checking , CTL( complex tree logic),LTL( linear temporal logic), assertion based verification. etc. U can find lots of tutorial about them on Internet. so have fun

 

[luancao]

It is a state-of-art process.

You know what is best. But you will have to reach a local optimal.

What is local optimal? It depends the resource available, the market requirement and also quality guideline.

Added after 4 minutes:

It is a state-of-art process.

You know what is best. But you will have to reach a local optimal.

What is local optimal? It depends the resource available, the market requirement and also quality guideline.

 

[narasimhalu]

Thanks for your information...
then in VCS what way can do verification other than the convenstional testbench..

with regards
R.Narasimhalu

 

[ldm]

........................

 

[luancao]

VCS 7.0 ( or some version like that ) or higher becomes what is called NTB ( Native testbench builder ). It integrate the Vera, system verilog, Direct C ...

U could build you testbench by these more powerful languages...