Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

can any one help me out plz.....

Status
Not open for further replies.

raki31

Member level 4
Joined
Oct 11, 2008
Messages
70
Helped
5
Reputation
10
Reaction score
2
Trophy points
1,288
Location
Hyderabad
Activity points
1,669
Wats d diff b/w GATE COUNT and PLACEABLE CELLS ?

thanks
 

you can find the answer in follwing book

VLSI Circuit Design Methodology Demystified: A Conceptual Taxonomy By Liming Xiu

You can download this book from net it is freely available

I hope you will get answer.
 

As my knowledge.....Gate count is how much transitors/ gates available in Design/Ckt/Standard cell......CELL's are contain's no.of gates...
......if u get ..any correct information ..pls ..fw to..me..

Thank's.......
 

hi,

my 2 cents

gate count is a rough prediction before the real place and route how much cells would be like
Total area / Nand2 area = gate count

Ths will give a rough idea, this is needed to estimate how big the chip would be, what would be the Xand Y and all..
but the value of the placeable instances would give an actual idea after place and route .

myprayers,
chip design made easy
https://www.vlsichipdesign.com
 

    raki31

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top