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On Xilinx Spartan3 FPGAs, the Xilinx PLL can function like a DLL. This means it can actively delay-match a reference-clock signal against an external 'feedback' clock-signal. This feature is important in DDR-RAM interfacing.
When I read the Cyclone II/III spec-sheet, I checked the Altera PLL for the same feature, but I couldn't find it. The ALTPLL seems to support 'source synchronous' or no delay control ... is that the same thing? In Quartus-II 7.1 (Web edition), I ran the Megafunction Wizard, and for the 'ALTPLL' device (in the I/O category), there is a greyed-out option for external feedback. That feature only turns on for the Stratix-II/III family.
When I read the Cyclone II/III spec-sheet, I checked the Altera PLL for the same feature, but I couldn't find it. The ALTPLL seems to support 'source synchronous' or no delay control ... is that the same thing? In Quartus-II 7.1 (Web edition), I ran the Megafunction Wizard, and for the 'ALTPLL' device (in the I/O category), there is a greyed-out option for external feedback. That feature only turns on for the Stratix-II/III family.