For level-sensitive storage element such as latch, data must arrive a certain minimum time befor clock goes inactive. A setup violation can cause invalid data to be captured by the latch or other level-sensitive device.
Hold time is the time for which the data for the next clock cycle shouldnot arrive or when put in other way, it is the time the data for the previous clock cycle has to be held(without changing) for it to be latched. A violation of hold time occurs when the data intended for the next cycle arrives early and there is a probability for the latch to store this data(intended for the next cycle) for the current cycle .
The need for setup and hold test is because the clock signals are not ideal in the sense they don't have a sharp rise or steep fall. That is the clock pulse doesnot suddenly disappear at falling edge arrival time or doesn't suddenly appear at the rising edge arrival time due to slew tranistion time.
Interval between the setup test and hold test is a timing "region of uncertainity". If the signal arrives in that interval, it might or mightnot get stored into storage element on that cycle
Therefore we must ensure that no data arrives during that interval.
So whether its a flip flop or a latch, SETUP TIME and HOLD TIME are applicable.
Look for the figures in the attachment below.