Calling VHDL procedures

[shaiko]

Hello,

I wrote 2 sequential VHDL procedures:
procedure_a.
procedure_b.
I want to call them from my testbench.
For example:

1.Call procedure procedure_a.
2.Wait for 100ns.
3.Call procedure procedure_b.
4.Wait for 100ns.
5.Call procedure procedure_a.
6.Stop here.

I tried to do it using a process as follows:

process 
begin
procedure_a  ( x , y ) ;
wait for 100 ns ;	
procedure_b ( x , y ) ;
wait for 100 ns ;
procedure_a ( x , y ) ;
null; 
end process ;

For some reason the testbench doesn't stop after the 3rd execution and continues infinitely...

Questions:
1. Why?
2. How to do it correctly?

 

[mrflibble]

VHDL noob here, so I'm extrapolating a little based on how stuff works in verilog.

1. Why not. ;-)

Simulation time doesn't magically stop just because you have an expectation based on "well, I'm done, you can stop now". That process still exists.

2. You want something like the VHDL equivalent of $finish.

See this thread: https://www.edaboard.com/threads/198782/

 

[TrickyDicky]

you need a wait statement at the end of the process, because all processes loop forever.

wait;