Calling tasks hierarchically in Verilog

[masai_mara]

calling tasks in verilog

Hi,
I wanted to know if I have tasks defined in a module, can I access those tasks by hierarchical calling mechanism in a different module. also what do these contructs mean in verilog-
event test_end;
@(test_end);
code..
code..
-> testcase_done;
what does the -> signify ?

thanks.

 

[vikasjn]

Re: calling tasks in verilog

Ya , u can call a task from anywhere hierarchially... the code u are referring to deals with the event emission ... please go through this section in any verilog book u will find the required information .