Calibre xRC C_CC: pmos parastic cap referenced to gnd instead of vdd

[beetwee]

I have a circuit with a large PMOS area consisting of current mirrors. Between the PMOS gate and VDD, there is a big capacitor, based on a pmos in pwell varactor (DNW underneath, pwell biased to vdd). Hence, the well of the PMOS and the capacitors are all biased to VDD.
When I run Calibre xRC, there is a lot of intrinsic cap ("C") to the specified ground node, as well as CC caps to the specified ground node. However, I expected that this should be referred to VDD, as the local substrate is all Nwell biased to VDD.

Trying to understand this, I made a simple testcase and found out that for calibre xRC, it doens't matter wheter I put nwell (biased to vdd) or not under a metal strip. The capacitance is always referenced to the ground node.

How can I solve this, as I cannot trust the AC results when parasitic cap in the PMOS area is grounded?

After reading the manual, I have disabled the options: ground all coupling capacitors and use the setting: extract floating nets: all.

 

[timof]

How extraction tool assign "ground capacitance" - i.e. capacitance from nets to the substrate / well - depends on several things.

First, there is a setting for "ground net" in all extraction tools.
Very often, people assign it to net VSS.
Then, you can't distiguish between the capacitances to metals/vias of net VSS, vsersus capacitance to well/substrate.
My advice and preference is to use an artificial net "0" for ground net.

Second, it matter how "well" polygons are treated in you flow - are they included into extraction vertical stack, and connect to real nets? If yes, then the capacitance to these well/substrate polygons will be counted as coupling to these nets. Otherwise - it will be counted towards "ground net" capacitance.

 

[AMS012]

You can include the following line in the PEX options:

PEX GROUND LAYER nxwell PSUB2 PSUB

nxwell, psub2 and psub is the order of preference for the extractor to refer the substrate cap to. This will make sure that parasitic cap in nwell region will be referred to the nwell.

 

[beetwee]

Thanks for your replies, they are very helpful.

When I set in the GUI gnd layer: nxwell psub, I get the expected results in a simplified layout experiment! Also the extraction of the pwell connected to vdd (for the pmos varactor) looks fine. The issue with the NWELL seems to be solved

When I use these settings on my circuit, I still see some CC cap to "0" (i did not specify a gnd node name). I think that parasitic cap from a DNW (biased to vssa) is not recognized yet to the correct node.

I use a triple well process from TSMC. I have a psub ring around my block, connected to the pin "vsub" which is only used for this ring. The DNW is biased to vssa, I have some resistors and nmos in this DNW. So I think I must add an additional layer to the gnd layer list for the DNW. In the ruledeck I found the following below, so I took the dnwc for the DNW. However, it does not solve that issue. Should I used another gnd layer for DNW (biased to vssa) or is the order important? This will probably give the same results as shorting the "0" node to gnd, but I think it is good to setup Calibre correct so that the output netlist is as close to the physical reality as it can be.

psub_under = psub_term OR DNW
dnwc = DNW AND nxwell
psub = BULK NOT NW
nxwell = NW NOT NWDMY

 

[timof]

This is really weird.
The precedence of the well layers (i.e. their order in the Z direction, and priority of assignment of ground capacitance to them), and their connectivity is usually defined in the LVS rule deck.
But Calibre mixes that into one SVRF file, combining LVS and extraction commands.

Should not this all be a part of standard PDK for your technology?
It may be dangerous to change things over there, you may get wrong results.

 

[AMS012]

This is really weird.
The precedence of the well layers (i.e. their order in the Z direction, and priority of assignment of ground capacitance to them), and their connectivity is usually defined in the LVS rule deck.
But Calibre mixes that into one SVRF file, combining LVS and extraction commands.

Should not this all be a part of standard PDK for your technology?
It may be dangerous to change things over there, you may get wrong results.

The reason for confusion with regards to the reference node of the parasitic caps is because of the substrate modelling. Substrate can never be modelled accurately as it would be in reality by calibre (or any other extraction tool for that matter), as the substrate is an infinite semiconducting plane. The extraction tool does not really identify correctly the local substrate layer for every device/metal layer that is underneath it, unless you force it to do so manually.

--- Updated Aug 2, 2021 ---

Thanks for your replies, they are very helpful.

When I set in the GUI gnd layer: nxwell psub, I get the expected results in a simplified layout experiment! Also the extraction of the pwell connected to vdd (for the pmos varactor) looks fine. The issue with the NWELL seems to be solved

When I use these settings on my circuit, I still see some CC cap to "0" (i did not specify a gnd node name). I think that parasitic cap from a DNW (biased to vssa) is not recognized yet to the correct node.

I use a triple well process from TSMC. I have a psub ring around my block, connected to the pin "vsub" which is only used for this ring. The DNW is biased to vssa, I have some resistors and nmos in this DNW. So I think I must add an additional layer to the gnd layer list for the DNW. In the ruledeck I found the following below, so I took the dnwc for the DNW. However, it does not solve that issue. Should I used another gnd layer for DNW (biased to vssa) or is the order important? This will probably give the same results as shorting the "0" node to gnd, but I think it is good to setup Calibre correct so that the output netlist is as close to the physical reality as it can be.

psub_under = psub_term OR DNW
dnwc = DNW AND nxwell
psub = BULK NOT NW
nxwell = NW NOT NWDMY

I guess, dnwc might not be the name of the deep nwell being used. If it is correct, then the problem should not arise.

 

[timof]

The reason for confusion with regards to the reference node of the parasitic caps is because of the substrate modelling. Substrate can never be modelled accurately as it would be in reality by calibre (or any other extraction tool for that matter), as the substrate is an infinite semiconducting plane. The extraction tool does not really identify correctly the local substrate layer for every device/metal layer that is underneath it, unless you force it to do so manually.

--- Updated Aug 2, 2021 ---

The wells and (epitaxial layer) substrate are usually doped high enough (> 1e16 cm-3) so that the static electric field is screened within a short distance, and does not penetrate deep into wells / substrate.

In this situation, the well that sits on the top of others takes all the capacitance.

This is a pretty good physical model for the substrate layers (I am talking ab0ut capacitance extraction - the resistance extraction in substrate is a much more complex thing, and there is no good tools to handle that easily and accurately).

The relative position in Z direction is well described by "precedence" mechanism, in layer setup file (map file).
Also, connectivity should be well described by LVS rule file, so that there is no ambiguity and no manual settings should be required in extraction.

This is in theory, and in good (i.e. complete) PDKs.
Many old PDKs ignored substrate, and manual intervention may be required - but only if the users know what they are doing.

--- Updated Aug 2, 2021 ---

"The extraction tool does not really identify correctly the local substrate layer for every device/metal layer that is underneath it, unless you force it to do so manually."

StarRC and QRC do that.
Calibre may not - too bad for Calibre and its users.