Calibre pex parasitic total resistance

[Daidai]

Hi,
I am running calibre PEX for parasitic extraction, I want to extract R+C+CC and the output format is Hspice
After finishing PEX, I look into the file about the parasitic resistances, there are many resistors show like:
.subckt XXXX%port1 1 3
r1 1 2 10
r2 2 3 5
Is there any method or setting that I can get the total resistance at port1 rather than so many resistors connected between different nodes?
or maybe the result combines all values by only two nodes like:
r1 1 3 15

I know you can get total C or CC in RVE, but it only gives ''resistor count'' not ''total resistance''

 

[timof]

"Total resistance" on R-extracted or on RC-extracted net is not a well-defined characteristic.

You need to understand how parasitic extraction works, what it does.

A net is fractured into polygons, resistance of each polygons is computed, coupling capacitances between nets are computed and assigned to the nodes of the R network, and a netlist for all parasitic R and C elements (also - with instances) is written out.
So, parasitic netlist is an RC graph so to speak.

You may be interested in measuring or calculating resistance form the port to device instance pin.
There may be many such instance pins - dozens, hundreds, thousands, or millions.
So, there are many "total resistances" on a net.

Tell us, which of these resistances are you interested in?
One of them some of them, or all of them?

You cannot sum up all resistors on a net, to get total resistance the same way as for the total capacitance - it just does not have a physical meaning.

 

[Daidai]

"Total resistance" on R-extracted or on RC-extracted net is not a well-defined characteristic.

You need to understand how parasitic extraction works, what it does.

A net is fractured into polygons, resistance of each polygons is computed, coupling capacitances between nets are computed and assigned to the nodes of the R network, and a netlist for all parasitic R and C elements (also - with instances) is written out.
So, parasitic netlist is an RC graph so to speak.

You may be interested in measuring or calculating resistance form the port to device instance pin.
There may be many such instance pins - dozens, hundreds, thousands, or millions.
So, there are many "total resistances" on a net.

Tell us, which of these resistances are you interested in?
One of them some of them, or all of them?

You cannot sum up all resistors on a net, to get total resistance the same way as for the total capacitance - it just does not have a physical meaning.

In my circuit, port1 is connected to the gate of a 2 fingers nmos.
So I want to get all of the resistances from port1 to the gate.
Does that mean I need to calculate the total resistance by myself?
I found P2P resistance in RVE, but I am not sure if it works correctly for port1 to the instance pins.

 

[timof]

In my circuit, port1 is connected to the gate of a 2 fingers nmos.
So I want to get all of the resistances from port1 to the gate.
Does that mean I need to calculate the total resistance by myself?
I found P2P resistance in RVE, but I am not sure if it works correctly for port1 to the instance pins.

So, you want to calculate the total resistance from the port "port1" to the gate of a multi-finger transistor - correct?

This is called gate resistance.

There are several ways how you can do it:

1. create SPICE deck, applying signals (voltages, curents) to port1 (i.e. ground it), and to gate instance pints (e.g. apply 1V to both instance pins). Run SPICE simulation, measure curremt (through port1), divide voltage by current, you will get the total resistance.

2. Automate all of the above using script and SPICE.

3. Use specialized EDA tools that will do that for you much faster, easier, and more insightfully - for example, they will tell you not only the total resistance, but also, contributions by each layer to the total resistance (such layers as as M1, via1, M8, AP, M0, via0, md, vg, gpoly, fpoly, etc.). It's very useful to know how much each layer is contributing to the total resistance - so that you know right away, what you need to work on, if your resistance is too large, and needs to be reduced or minimized. There are some EDA tools that will do much more for you, and show you the contribution from each polygon on the layout, so that you will see the bottlenecks, choke points, weak areas, etc. It saves a ton of time for you.

This article may be useful, for this topic:

Circuit simulation and parasitics: do we need more speed, or more insight (or both)?

I recently read John Cooley’s interesting article on the Troublemakers panel discussion at DAC 2020 between Mentor’s Joe Sawicki and Cadence’s Anirudh Devgan. They were talking about Mentor’s AFS-XT SPICE simulator beating Cadence’s Spectre-X in speed by a factor of 3x-10x.

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