Calibre LVS Mixed Signal Bulk ISSUE

[cheneyliu99]

lvs substrate

Hi All,

I am designing a mixed-signal chip. In my schematic, I used different pins for different signal's bulks. e.g. ASUBGND for analog bulk, PWR_SUBGND for Power circuit bulk, etc. When I do Calibre LVS, whenever I have types of signals, LVS will not let me pass. The reason is that, physically, all these pins share save p-substrate layer.

Is there any way that I can pass the LVS without too much modification. e.g. adding some rule file for LVS saying that ASUBGND equals to PWR_SUBGND etc.?

Or do I have to modify the schematic?
Thanks!

 

[JoannesPaulus]

mixed signal lvs

you need to add a new layer in your layout, generally called PSUB2. This layer defines a different substrate region (even though they are all connected together).

 

[cheneyliu99]

JoannesPaulus

It is a really nice and simply way.
I am using AMIS PDK, the corresonding layer is called MSUB.

It works well!
Thanks a lot! !

 

[prashantbabu]

Hi cheneyliu99, please know that psub2/msub is just a dummy layer used to clear LVS. Since it is not a physical layer, the ASUBGND and PWR_SUBGND are effectively shorted.
In case you do need isolation between the two, you need to use deep n-well layer.
If you are using ASUBGND for mixed-signal blocks, it is bound to be noisy. If you are using PWR_SUBGND for any sensitive power circuits like a BGR or any bias blocks, then the noise on ASUBGND will short to PWR_SUBGND.