[SOLVED] Calibre LVS issue(gate length property error)

[guruprasadds]

Hi Friends,
Im running calibre for my LVS 28nm digital design, Im getting property errors with mismatch in gate length and with with max 1.56% and .06% difference respectively in layout vs schematic.
Can any one help me to resolve this? im confused about what value and where to set in rule deck.
tapeout is 5 days away so please some one help me.

 

[erikl]

im confused about what value and where to set in rule deck.
tapeout is 5 days away so please some one help me.

I don't think you'll get a "go" if you change the rules deck. Better readjust W & L in your schematics!

 

[DharmaSlice]

There is a variable in most decks that set the tolerance

---The Default setting for property check is 0%. Users should check with IP/Design providers for proper tolerance.

Do a search for "tolerance" in your rule file and it should tell you how to set the default from 0% to a higher value.

 

[guruprasadds]

Hey Erikl and Dharmaslice,
thanks both of them for the reply. I resolved it. Problem was it was comparing wrt 4th significant digit. You can look in to the error image i have attached.
the digits in source and layout are 3 and 4 respectively.
So i enabled HIGH_RESOLUTION switch in rule deck, enabling ll compares upto significant digit. I think looking into Rule deck n that switch may make u guys understand the issue.

Thanks
Guru