Counter:
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-- hds header_start
--
-- VHDL Architecture calculator.counter.untitled
--
-- Created:
-- by - Asmaa.UNKNOWN (IDEA-PC)
-- at - 09:47:55 10/04/2015
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee ;
USE ieee .std_logic_1164 .all ;
USE ieee .std_logic_arith.all ;
ENTITY counter IS
-- Declarations
port ( clk,rst,en: in std_logic ;
count: out std_logic_vector ( 3 downto 0 ) ) ;
END counter ;
-- hds interface_end
ARCHITECTURE untitled OF counter IS
signal count_temp: unsigned ( 3 downto 0 ) ;
BEGIN
process ( clk,rst)
begin
if ( rst= '1 ') then
count_temp<= ( others => '0 ') ;
elsif ( rising_edge( clk) ) then
if ( en= '1 ') then
count_temp<= count_temp+ 1 ;
end if ;
end if ;
end process ;
count<= std_logic_vector ( count_temp) ;
END untitled;
MUL4_1:
LIBRARY ieee ;
USE ieee .std_logic_1164 .all ;
USE ieee .std_logic_arith.all ;
ENTITY Mul4_1 IS
-- Declarations
port ( a: in std_logic_vector ( 3 downto 0 ) ;
sel : in std_logic_vector ( 1 downto 0 ) ;
y: out std_logic ) ;
END Mul4_1 ;
Dec2_4:
LIBRARY ieee ;
USE ieee .std_logic_1164 .all ;
USE ieee .std_logic_arith.all ;
ENTITY dec2_4 IS
-- Declarations
port ( a: in std_logic_vector ( 1 downto 0 ) ;
y: out std_logic_vector ( 3 downto 0 ) ) ;
END dec2_4 ;
-- hds interface_end
ARCHITECTURE untitled OF dec2_4 IS
BEGIN
process ( a)
begin
if ( a= "00" ) then y<= "0001" ;
elsif ( a= "01" ) then y<= "0010" ;
elsif ( a= "10" ) then y<= "0100" ;
else y<= "1000" ;
end if ;
end process ;
END untitled;
Nodpad:
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-- hds header_start
--
-- VHDL Architecture calculator.nodpad.untitled
--
-- Created:
-- by - Asmaa.UNKNOWN (IDEA-PC)
-- at - 09:58:08 10/04/2015
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2001.5 (Build 170)
--
-- hds header_end
LIBRARY ieee ;
USE ieee .std_logic_1164 .all ;
USE ieee .std_logic_arith.all ;
ENTITY nodpad IS
-- Declarations
port ( Key_pressed: in std_logic_vector ( 4 downto 0 ) ;
rows: in std_logic_vector ( 3 downto 0 ) ;
cols: out std_logic_vector ( 3 downto 0 ) ) ;
END nodpad ;
-- hds interface_end
ARCHITECTURE untitled OF nodpad IS
BEGIN
process ( rows,Key_pressed)
variable cols_var: std_logic_vector ( 3 downto 0 ) ;
begin
cols_var:= "0000" ;
if ( key_pressed( 4 ) = '1 ') then
cols_var( conv_integer( unsigned ( Key_pressed( 1 downto 0 ) ) ) ) :=
rows( conv_integer( unsigned ( Key_pressed( 3 downto 2 ) ) ) ) ;
else
cols_var:= "0000" ;
end if ;
cols<= cols_var;
end process ;
END untitle
Last edited by a moderator: May 13, 2015