Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Calculating the maximum op frequency of a design

Status
Not open for further replies.

jaseel_abdulla

Newbie level 4
Joined
Aug 13, 2007
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,326
Hello..

Any one having any good doc regarding calculating the max op frequency of a design, explaining topics like -ve set up time, -ve hold time, timing violation etc.

Plz reply...

plz send ur docs to

clickonjaseel@gmail.com

Thanks
Jas
 

avimit

Banned
Joined
Nov 16, 2005
Messages
413
Helped
91
Reputation
182
Reaction score
23
Trophy points
1,298
Location
Fleet, UK
Activity points
0
Re: Help!!

Well, I can only say:
Fmax = 1/(Tsu+Tpd+Ttc)
Well make it simple I have not considered skew.
Where
Tsu = Setup Time of FF
Tpd = Propagation delay of the FF
Ttc = Delay of the combinational logic between the FFs.(This would be of the worst combi delay in your design)
Kr,
Avi
https://www.vlsiip.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top