Calculating Length-matching requirement for DDR2

[nelsonys]

According to i.MX53 datasheet, we have to route Add, Data and Control signals within +/- 25mils of the length of the clock for the correct latching.

I wonder how can we calculate out this value.
and how do we implement it?

Say we route clock signals first and get the largest possible length of it then do some calculation by substituting in which formula??

 

[loosemoose]

These tight tolerances are given in order to minimize the skew within the group. +/-25mils is equivalent to ~10ps timing skew.
There is a max. length to the first dimm and another max. length between the dimm's them self. you also need to consider load and termination.
The official spec's for DDR2 are JEDS79-2E from Jedec.

I don't understand what value do you want to calculate.

 

[buenos]

The lenght matching rules come from timing calculations, that was done by the guys at Freescale.
Anyway, about how to do such a thing, check this:
https://buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls

 

[nelsonys]

Thanks Loosemoose and Buenos...

I just don't have the concept of calculating the skew budget for DDR2 board trace.
Instead of considering flight time, it seems like we need to take into consideration of setup and hold time according to Intel's note.

---------- Post added at 17:44 ---------- Previous post was at 17:43 ----------

Thanks Buenos for your excel file, it's an amazing work indeed!