Calculate parasitic before layout in UMC 0.18 process?

[Grecs]

I am interested in creating a design that takes into account capacitance parasitics in some nodes of the circuit. How am I supposed to know the parasitics roughly before the layout? Is it ok if I just use a grounded capacitor in connection with that node? And what is going to be its value??? I dont want something very accurate I just need something to get started.

 

[erikl]

I am interested in creating a design that takes into account capacitance parasitics in some nodes of the circuit. How am I supposed to know the parasitics roughly before the layout? Is it ok if I just use a grounded capacitor in connection with that node? And what is going to be its value??? I dont want something very accurate I just need something to get started.

I think for a 0.18µ process this could result in a rough but quite good first-order estimation. Essentially use the wire connection (routing) capacitances. The PDK should give you the appropriate cap/metal-area values.

 

[Grecs]

The parasitics I am seeking (without any success), are those from a metal 1 node to the substrate (the capacitance). Is there anyway to find that? Is it some pF or fF? Is it Cox * w * L of the wire?

 

[erikl]

If you can't get these values from UMC, you could e.g. use these published values from a (size-wise) similar process (scroll down to CAPACITANCE PARAMETERS).

Should be good enough for approximate parasitics. Your equation is correct. For even more accuracy, don't forget the fringe contributions.