patricky
Junior Member level 1
For Cadence layout, do you guys like to generate layout cells from schematic via Virtuoso XL, or prefer to instantiate your own cells and then manually correspond the devices in schematic with the layout?
For me, I have had trouble mapping multiple devices in schematic with my designed multi-fingered (interdigitated) transistors in layout, or at least Virtuoso would not allow me to do so, making LVS checking tough. Thanks in advance for any input.
For me, I have had trouble mapping multiple devices in schematic with my designed multi-fingered (interdigitated) transistors in layout, or at least Virtuoso would not allow me to do so, making LVS checking tough. Thanks in advance for any input.
