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Cadence Virtuoso Post-layout simulation using Calibre

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hellotheworld

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Hi !

I am struggling in post-layout simulation using Calibre.

My layout passed drc, lvs and pex. Then, I created another schematic to form a new circuit including power sources and a symbolized instance.

it went to post-layout simulation by creating config and set the instance as "Calibre" in Hierarchy Editor.

After running post-layout simulation was completed, the magnitude of the output voltage is zero which is totally different in schematic simulation.

How to fix this problem?

Thank you!
 

In earlier times you would invoke the "analog_extracted"
view, which was "refined" from the "extracted" view (for
what, how, I do not know, but there was that step to do).

If "caliber" view is what replaced "lvs" view then that
would not be the appropriate view for a simulation
netlist. Stop-view should either be "spectre" or "veriloga".
 

Thank you for your reply.
When I created config, I used the spectre template.
I also tried to run post layout simulation in schematic view. In ADE, I added a word "calibre" in environment but it was unsuccessful. The CIW said "(OSSHNL-912 ) netlisting failed because terminal 'vdd!' ...".
I don't know whether is my layout design problem or others.
 

How did you create the Calibre View? It is created automatically by Calibre View Setup Menu, did you populate the Menu correclty?
 

This problem was solved. I changed all pin names to capital letters, e.g. vdd! --> VDD, vss! --> VSS. Then, running the post-layout simulation was successful. But I don't know why it works.
 

Pins with a ! suffix are automatically "global"
while your all-caps, no-punctuation pins are
not.

You can't get a good post-layout netlist
without a passing LVS.

So maybe you have a broken net that is
made continuous in one view but not in
the other, like a hairline gap in what you
-think- is a continuous "vdd!" bus but only
one pin placed, so the "global" pin does not
get to define what you think is the entire net.
Probing might show that.
 

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