cadence VHDL AMS - ERROR (OSSHNL-116)

Hi everyone,

I have a cell "resistor" described in vhdl ams. It compiled fine and created 3 cell views : entity, behavioral and symbol

I implemented the "resistor" symbol in a new cell schematic "xbar"

I am trying to simulate this schematic using spectre in ADE L but I have this error during the netlisting :

"
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'I0' in cell 'xbar'. Either add one of these views to the library 'newone',
cell 'resistor' or modify the view list to contain an existing view.

End netlisting Mar 22 14:15:10 2012
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be corrupt
or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
"

I have been trying to figure out a solution but cant really find one.

Do you guys have an idea?

Thanks for helping,

david