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Cadence Spectre Simulation Problem

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wuZheng

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Hello all,

I searched up Google for a solution to my current problem which redirected me here, but the response given was far from adequate, asking the OP to simply check their current design did not give much insight into fixing my own problem.

PROBLEM:
Spectre spits out this error for a design I'm working on:

ERROR (SPECTRE-16386): M3: Too many terminals are given.

M3 is a transistor as you can imagine using some proprietary technology library. It has exactly 3 terminals (4 if using the alternate), there are exactly 3 lines attached to it. To make sure I wasn't going crazy or that the design somehow influenced this error, I went around and created a new design file.

The new design has a single transistor, a variable source connected to the gate, VDD to drain, and source grounded (as well as the base using the alternate symbol). Again I get this error:

ERROR (CMI-2117): M0: Too many terminals given (6 > 3).

I am truly stumped as to what would be causing this error, if anybody has any insights, it would be greatly appreciated. Thanks.
 

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