Cadence & Sizing of Capacitor for Layout

[KPotter999]

Dear Group,

I am completely new to Cadence and AMS for layout but have been given an assignment to design a Butterworth filter and had various questions regarding capacitors.

I am using the following tools:

Cadence 5.1.41
AMS C35B4C3

Due to caonstraints I am looking to implement capacitor values up to 10pF maximum and resistor values up to approx 350 KOhms.

I am attempting to use Cadence layout to compare area combinations of capacitors and resistors to get a feel for a good trade off. However, I dont know how to calculate the capacitor area because:

1. How do I find the relative constants such as mobility, Oxide capacitance etc for Austria Micro Systems 0.35um technology?

2. I have used virtueso schematic and see that values can be entered for the capacitor W and L, but is there a way to have the tool automatically provide sensible sizing?

3. Many people discuss unit area and 'Lambda' in terms of layout and say that if you layout in an S shape you need to consider 0.5*Lambda layout rules, is Lambda=0.35um for a 0.35um process, everyone talks about Lambda but no one explains what it is.

4. If I have to layout the capacitor using Layout XL, can Cadence verify what the capacitance of the design is?

Apologies if this is a repetitive questin on the forum or if these questions really are basic but I really have not found much help on the MOSIS website and would really appreciatte your input!

Kindest regards,

Ken Potter.

Added after 1 hours 14 minutes:

Dear Group,

Since I cannot find the process information for AMS 0.35um, can anyone confirm if the following assumptions are correct?

Oxide capacitance typically 4.3fF/um^2 for 0.35 BULK, based on 7nm oxide thickness.

Double poly capacitors have an oxide capacitance which is half of this value
Metal sandwich capacitors have 1/20 of this.

Secondly, regarding resistors is 140 Ohms/Square reasonable for unsilicided poly resistor and how do you know if the process allows for silicided or unsilicided poly?

Thanks, Ken.

 

[erikl]

... 1. How do I find the relative constants such as mobility, Oxide capacitance etc for Austria Micro Systems 0.35um technology?

See the PDF below, p. 2 (bottom).

4. If I have to layout the capacitor using Layout XL, can Cadence verify what the capacitance of the design is?

Sure.

Added after 1 hours 14 minutes:
Since I cannot find the process information for AMS 0.35um, can anyone confirm if the following assumptions are correct?
Oxide capacitance typically 4.3fF/um^2 for 0.35 BULK, based on 7nm oxide thickness.

Cf. **broken link removed**

Secondly, regarding resistors is 140 Ohms/Square reasonable for unsilicided poly resistor and how do you know if the process allows for silicided or unsilicided poly?

See your PDK docu.

 

[KPotter999]

Hello,

And thank you for the response, the PDF looks excellent! Just one question however, how do I obtain the PDK document because I am a University student and do onot have direct acees to the MOSIS website and have not seen any supporting documentation on the University website.

Many thanks, Ken.

 

[erikl]

... how do I obtain the PDK document

I got it from some posting in one of the EDAboard forums (don't remember from which one). :-(

... do not have direct access to the MOSIS website and have not seen any supporting documentation on the University website.

See e.g. here.