Cadence Simulation: Help Needed

[sankudey]

Hi,
While simulating in Cadence Analog Design environment, I face the following problem. Any help would be of great value.
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Problem Description:The transistor count is approx. 5000 (7-bit ADC) for the circuit I want to simulate by spectre. I gave a "transient" simulation ("tran") from analog design environment for a period of ~ 525ns while the operating clock/signal is ~ 2.5GHz. The simulation is completed "successfilly" but the output shows that upto only 114.9ns the outputs are OK but there after all the voltage and current signals are straight line and bearing garbage value.
Please advice me for the same.
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Thanking in Anticipation
sankudey

 

[BigBoss]

Have you checked the output options ??Because if all outputs are saved , the result file can explode and rest of the time may be seemed empty..

Save only the nodes and currents that you're intersted in..

It can also be a memory problem..

 

[sankudey]

Hi,
I have tried out the option u have suggested. To explain it a little more....it seems to me a problem of memory. But definitely the problem is not from RAM or HARD DISK. Its like this.

For a particular complexity (say tarnsistor count ~ 2000); whatever be the option is the valid zone of output is same and for all cases the tran.tran (the output data file) is having the same size (~ 1GB). But the RAM is 4GB and hard disk available for simulation is 70GB.
Now when the complexity got increased (transistor count ~4000) the valid zone comes down with tran.tran size ~2GB for all cases.

From the above thing what I can conclude is it is related to memory and also the total no. of steps along with the complexity. U can see the for even lower cpmplexity the tran.tran size is not same as for higher complexity. May be some where some option is there that I don't know. But what u told is not wotking.

If anyone can tell some other option would be of great help.

sankudey