Cadence Power Analysis: VCD - Problem

[Locke]

cadence power analysis

Hi all,

i'm trying to get power characteristics for a design, based on a VCD-file. The VCD is created with Synopsys VCS. I use the Cadence SoC Encounter platform for power analysis. When SoC Encounter reads the VCD-File, the following messages are shown:

*** Processing VCD file (cpu=0:00:00.0 mem=195.5M) ***
power supply: 1.2 volt
averaging power between 0 and 7.5e-08
vcd total id_reference: 4235
    valid id_reference: 0
    invalid id_reference: 2379
    redundant id_reference: 1856
vcd total activity: 7912
    valid activity: 0
    invalid activity: 7912
average power(default) : 4.7114e-03 mw
    average switching power(default): 0.0000e+00 mw
    average internal power(default): 0.0000e+00 mw
    average leakage power(default): 4.7114e-03 mw
    user specified power(default): 0.0000e+00 mw
average power by cell category:
     core: 4.7114e-03 mw
    block: 0.0000e+00 mw
       io: 0.0000e+00 mw
*** Power analysis (cpu=0:00:00.2 mem=195.5M) ***
The net voltage for GND is 0V.
Delay calculation ...
*** End delay calculation ***
*** Delay calculation (cpu=0:00:00.2 mem=195.5M) ***
Analyzing vcd vectors:

*** Processing VCD file (cpu=0:00:00.0 mem=195.5M) ***
power supply: 0 volt
averaging power between 0 and 7.5e-08
vcd total id_reference: 4235
    valid id_reference: 0
    invalid id_reference: 2379
    redundant id_reference: 1856
vcd total activity: 7912
    valid activity: 0
    invalid activity: 7912
average power(default) : 4.7114e-03 mw
    average switching power(default): 0.0000e+00 mw
    average internal power(default): 0.0000e+00 mw
    average leakage power(default): 4.7114e-03 mw
    user specified power(default): 0.0000e+00 mw
average power by cell category:
     core: 4.7114e-03 mw
    block: 0.0000e+00 mw
       io: 0.0000e+00 mw
*** Power analysis (cpu=0:00:00.2 mem=195.5M) ***

What is wrong with my VCD-File. Any Idea???

Thanks in advance

 

[elvishbow_zhl]

average power cadence

I think maybe it is because your VCD file generation wrong.
You see there are no switching information can be read from your VCD file. You can check your testbench and regenerate the VCD file.

 

[Locke]

power analysis vcd based

This is what I thought, too. So I tried out NC-Verilog for simulation but with almost the same result. Now, power analysis finds 4531 instead of 4235 id_references, where 1431 are invalid and 3100 are redundant. Is there anyone, who can tell me generally what id_references are? A solution of the whole problem would still be appreciated, of cause.

 

[ttspice]

power with vcd file cadence

you can view the VCD file, it's a text. you will find it declares cells, ports, signals in hierarchy. If the top cell name is wrong, then all nodes can not been matched with the netlist. you can dig out this problem by comparing the vcd dumped by NC-vlog and VCS.

 

[haifengyuyun]

power analysis with vcd

how accuracy is it when simu power by socencounter when compare to chip real work?

 

[haifengyuyun]

cadence vcd

and how u used pks to simulation power?

 

[skymusic]

average switching power(default):

You can check if the hier is consistent.