[<Cadence>] Palladium Questions

[ivlsi]

Hi All,

I have a couple questions about Cadence's Palladium (1, 2, or 3 - no matter).

1) What's inside of Palladium? FPGA boards or just powerful CPU's?
2) Why there is the clock speed limitation (up to 10MHz for P3)? No PLLs could be simulated?
3) As for the TestBench, is it also run on Palladium (compiled there). Should it be synthesizable as RTL?

Thank you!

 

[jbeniston]

1) I believe some versions use their own dedicated ASIC. I'd imagine it's a bit like an FPGA, but more suited to this task.

 

[ivlsi]

Re: [&amp;lt;Cadence&amp;gt;] Palladium Questions

like an FPGA

Probably, but I'm not sure 100%. Cadence doesn't say these are FPGA. So, I suspect they are some powerful CPUs, but again I'm not sure 100%.

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If FPGA there, then what are FPGA (Xilinx?Altera?others?)?
As for TestBench, does it run on user workstation or on Palladium itself?

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Why working frequency so slow (up to 10MHz)?

 

[jbeniston]

Re: [&amp;lt;Cadence&amp;gt;] Palladium Questions

They're aren't FPGAs from Xilinx or Altera. They are dedicated ASICs. What I mean is, the ASICs are probably similar internally to FPGAs, but more suited for emulation.