Cadence LVS label shorts in Pcells?

[jgk2004]

Hello all,

I have LVS label shorts in my Pcells and can not find a way to remove them. My DRC is clean and my LVS says Layout matches schematic. But I have label shorts... I can also generate an extracted view and my top level simulates perfectly.

Can I ignore label shorts?

Also I have been finding I have alot more label shorts when I use the constraints manager? Is there any correlation? It seems the more layout constraints I have the more I see of these label shorts......

Thanks for any help

JGK

 

[deepak242003]

if you can add layout view and report file summary.. sum1 here could help you

 

[analogjeannie]

which tool r u using..?

 

[jgk2004]

I am using Assura.

Added after 1 minutes:

Deepak, what is the exact name of the file you would like to look at?

Thanks

JGK