cadence layout metal width (in high current, in long wire)

[goatmxj666]

Hello

Q1.
I'm doing layout the charge pump, but I don't know how thick the metal should be.

I read that 1um/1mA is good, but is the same applied to MOSFETs using fingers? The total width of one of my pmos is 300um. (length=minimum, finger width=5u, fingers=10) * 6

The peak current flowing through the MOSFET and capacitor of the charge pump is 10mA (with no load). When connected to a load, ~50mA flows. Then, should the width of the metal be 40um? (with load)
I think it can be made thinner because fingers are used.
Q2.
What is the good metal thickness of a long wire? (VSS, VDD) ex. over 500um

 

[kemiyun]

Q1: Refer to your PDK. 1um per 1mA is a rule of thumb thingy, it's not always correct for all the processes. Your PDK would have a section for metal current density rules and they usually report RMS and peak density each metal layer can handle separately. For example a metal layer that can handle 1mA per um width can handle a lot more if it's only transient. Electromigration is one of the keywords you're looking for.

FETs are usually not more conductive than metal for the same width so it's often not an issue. But they also have limitations. Usually your resistance requirement for a switch for example would drive the FET size rather than current carrying capacity.

Q2: It depends. You need peak and average current profiles to be able to decide it. And don't forget to simulate all the downstream circuits with the added resistance from the routing. Decide based on circuit level limits and the physical limits of the metals.

 

[dick_freebird]

You have to look at cross-section-in-play at every step
of the way.

Fingering helps. So does pulling current up through
multiple vias onto traces routed perpendicular to width.
If you have terrible contact step coverage then this is
better than pulling current out the end because the last
contact on the way out, is a severe choke-point to all
the others further in. If your contact is allowed to be as
wide as min metal then you could see heinous cross
sectional area reduction at the contact sidewall, times
two, every one of 'em. That's a fail waiting to happen.

Visualize it as plumbing with a variety of pipe diameters
and this may lead you to "points to ponder". Anywhere
the metal width, metal layer or current changes, you
have to either disposition (e.g. any current below the
mA for min W for layer, you get to check off) or analyze
until you have collected all cases, to select the worst
(declaring success if passing Jmax) or fixing the layout
where not.

Long lines are not different than short as long as you're
above the Blech length (where mass migration does not
occur, below). These are what EM rules will be derived
from.

If you were conservative you might go as far as to study
the reliability reports(if accessible) to see how proper the
experimental conduct and analysis were. Seen some
on that count. Like running so much forcing current that
a conductor would be high above ambient, but using oven
faceplate temp for analysis. I had to follow ridiculous Met2
rules for years until I could convince somebody to read my
damn memo showing all that. Then they just let me use
industry (MIL) standard Jmax instead, never did anyone
go and repeat the reliability experiment. Lazy lying bastages.

Depending on customer / end-use you may receive more or
less attention to your methods and results. Heads up.

 

[ljp2706]

Hello

Q1.
I'm doing layout the charge pump, but I don't know how thick the metal should be.

I read that 1um/1mA is good, but is the same applied to MOSFETs using fingers? The total width of one of my pmos is 300um. (length=minimum, finger width=5u, fingers=10) * 6

The peak current flowing through the MOSFET and capacitor of the charge pump is 10mA (with no load). When connected to a load, ~50mA flows. Then, should the width of the metal be 40um? (with load)
I think it can be made thinner because fingers are used.
Q2.
What is the good metal thickness of a long wire? (VSS, VDD) ex. over 500um

For long wires that carry significant current thickness is usually not limited by electromigration. You need to assess what the maximum tolerable IR drop is on the line and then size the width to be less than that. I like to do a parametric sweep of resistance on the supply and monitor some key parameters. You can plot the derivative of the parameters to see at what resistance that parameter starts falling off rapidly. Using sheet resistivity and line length, you can backtrack how wide it needs to be since you know what your current is and max tolerable voltage drop.