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Cadence Layout (LVS error in bulk connections)

J.H

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HI!
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Is it possible to implement in layout a bulk that is connected to its own source (not connected to VDD or GND)? I have a hard time implementing this in layout because whenever I hanged a separate guard ring for the device(with the bulk connected to source), LVS would always give me softcheck errors. Can anyone enlighten me on this?? Im really stucked. I need some references to look into to investigate further.
 

shlooky

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Hi there,

PMOS transistor is usually located in NWEL, which is also its bulk connection. PMOS is therefore isolated from common substrate and the bulk connection can be shorted to the Source terminal or any arbitrary potential as long you keep the diode between NWELL and substrate in reverse bias.

NMOS transistors NEED to have their bulks on the lowest potential, since they are located directly in common substrate, which is connected to the ground. So, in your schematic... you either need to use isolated NMOS devices (which requires twin-well or triple-well technology). The cost, in this case, is an increased silicon area, but you can bias the NMOS bulk to any potential as long you keep the diodes between substrate and isolated bulk of NMOS in reverse.

The other option (most common) is you connect all bulks to the ground. This step will offset your threshold voltages in stacked transistors and might change the circuit behavior, but if I understand correctly you do not want this....

Shlooky
 

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