Cadence, how connect this gate

[pat_fr]

Hi all,

How can I connect his gate ?
I can't put my via1 on the top of the gate, it's too small and I can't connect my via with en poly1 path. I have this error :
Minimum PPLUS to NPLUS spacing on POLY1 = 0.25 :?

Any idea ?

thanks

 

[renwl]

Is it the standard cell from pdk? why not layout a new one?

 

[road_0506]

try to remove contacts and cut metal in the guard ring... thereby allowing u to use first metal for wiring...

 

[safwatonline]

i am no layout expert but why not extending the poly out then do whatever u want

 

[renwl]

I am also confused now.
maybe it's not a problem about via.
it's a problem about PPLUS and NPLUS,isn't it?

 

[cougar168]

please post your GDSII file

It is too small to make it out

 

[pat_fr]

thanks for your reply

Is it the standard cell from pdk?

pdk ? what is it ? It's just a standard nmos4 with a guard ring

try to remove contacts and cut metal in the guard ring...

How can I do ? I can disable the right guard bar and connect my via but how can I close the guard ring ?

i am no layout expert but why not extending the poly out then do whatever u want

i can't, i have an error like the joined file

it's a problem about PPLUS and NPLUS,isn't it?

it is

please post your GDSII file

What is it ?
I am a beginner in layout and in english too

 

[williamy]

enlarge the guard ring

 

[srikanth_476]

abut P+ and N+ so that u won't get that violation

 

[road_0506]

make P+ to N+ distance equal to zero...

 

[laglead]

through metal1