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cadence error running verilogA (SPECTRE-18): Segmentation fault.

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RamyRady_RF

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Hello,

I was trying to rerun the same verilogA code again, but I face this error:

Internal error found in spectre during AHDL read-in, during circuit read-in, during hierarchy flattening,.
Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the Spectre log file, the behavioral model files, and any other information that can help identify the problem.
FATAL (SPECTRE-18): Segmentation fault.

any suggestions?

Thanks
 

RamyRady_RF

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it is indep. of the code, even a cap from ahdLib, or any other veriloga cell
 

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