sharted,
my design is special data coder core with LVDS and ring oscillator for clock sourcing. Clock source (RO, LVDS) is selected by multiplexer. There is only one clock in design core, and I need to maximize clock frequency without setup/hold violation involving. This is the signature of digital core module:
module coder(C, CP, R, GP, D, VD, START, Q, QEND, QKF, QTR);
input C, CP, R, GP, D, VD, START;
output [18:1] Q;
output QEND, QKF;
output [4:1] QTR;
endmodule
The C input is clock signal, I synthesize clock tree for it.
My SDC file is:
create_clock -name "CLKFAST" -add -period 10.00 -waveform {0.0 5.00} [get_pins {cs/C}]
set_clock_gating_check -setup 0.0
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/ADFM0NA]
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/AN2M0N]
set_dont_use [get_lib_cells uk65lscsp10bbrccs_100c25_tc/AN3M0N]
etc...
When I sumulating my final netlist with MAXIMUM delays I see some SETUP errors along with HOLD too.
I suppose my SDC is incomplete, and this is the reason of design timing problems. In this case, what I need to add to my SDC file?
Thanks in advance,
Kuxx.