Cadence ELC. Problem with flip-flop and latch.

[vermut]

Hello!
I am using Cadence ELC to characterize a new standard cell library. Combinational cell characterized well, but I have problem with flip-flop and latch:

elc> db_gsim -f

Reading : SOI025_2.ipdb/latnrs_1.design

==============================
DESIGN : latnrs_1
==============================
- illegal net ( d1 ) is found [ 3 drivers ] :
[1]:not [2]:not [3]ushpull
- illegal net ( d2 ) is found [ 2 drivers ] :
[1]:not [2]mos

=> no simulation

================================
stimulus generation summary
================================
Name #MOS #DVEC #RVEC
----------------------------------------
latnrs_1 27 0 0 *
----------------------------------------
0 0


Can anyone please help me, I am not sure what the problem is

thank you

 

[simopoulos]

I am facing the same problem with my RS_LAT.

Is there a way to walk this through?

Thanks.

 

[eklikeroomys]

Yes, ELC will not be extract functionality for these cells from the netlist.
You will have to write a gate file for each cell like this. ELC will then be able to extract functionality from the gate file.
For information on gate files, see the ELC documentation.