Cadence-Digital ASIC design flow

[ksrinivasan]

Guys
iam doing a digital ASIC design project. Can somebody tell me what are the tools that i require for a complete flow from RTL to GDS II flow.Iam currently trying to work with SOC encounter.Is this tool alone enough or should i have design compiler and some more tools.Looking forward for ur early help

Thanks
Srinivasan

 

[ljxpjpjljx]

for simulation you should use ncsim!

 

[nschiku]

Functional Simulation --> IUS
Linting/Other Checks --> HAL
Synthesis --> RTL Compiler
Formal Verification --> Conformal
Timing Analyis --> Encounter Timing System
DFT --> Encounter Test
Physical Design --> SOC Encounter
Physical Verification --> ASSURA

 

[ksrinivasan]

Soc enocunter does the complete RTL to GDSII flow...
so downloading soc encounter alone is sufficient..am i right

 

[vlsichipdesigner]

hi,

my 2 cents,

At first you need to know the complete asic design flow,

There are pointed tools available for performing specific task if you need accuracy , you can get the list of the tools and their datasheets, and what functionality or what portion of the asic design it will be covering can be found at the EDA vendor portal for example visit, synopsys/cadence/mentor browse through them , there are hundreds of EDA vendors, thousands of tools available, on the need basis, it is hard to genarlize.

myprayers,
chip design made easy
https://www.vlsichipdesign.com