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Cadence Assura DRC error

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sami786

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minimum top via enclosed by metal top 1 is 0.01micron... How to fix this error.. I am using 8Metal layer process? It appears when i place metal 6 and Top metal via top.
 

min. top via is 10nm ??? Which process size? Typo?
 

erikl said:
min. top via is 10nm ??? Which process size? Typo?
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I think the enclosure has to be 10nm wider than the via. either way, OP should post the actual error msg, not his interpretation of it.
 

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