Cadence Annotation Brower illegal weak connections

[jgk2004]

Hello all,

I am designing in TSMC 90nm and have a question about blinking blocks in my layout.

I have opened up the annotation browser and it says I have weak illegal connections. But I am DRC and LVS clean and can generate a parasitic extraction with no problems. My extractions also simulate perfectly in my toplevel.

But do I need to worry about this errors from the annotation browser? I would think DRC is all I need!

The errors are coming from my MIM caps. The Mim caps top metal are in M8 and I am just connecting to the correct area and viaing down to M2 or M3 or M4. I also using between 4 to 10 vias so its not like I am not using enough...

Any help would be great!

Thanks

JGK

 

[jgk2004]

I am still looking for any info on these illegal connections.... I did tapout the chip and it functions correctly. I would just like to know why this "browser" is showing Illegal connections....... Does anyone in industry use this damn thing?

Thanks
JGK