# Cadence AMS - connect rules

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#### atamez

##### Newbie level 6
amsconnectlibcompile

update - i found the library connect_lib and amsConnectLibCompile, and I believe I have installed the new library correctly.

However, now during elaboration I get the following error:

ncelab: *E,CUVNCM (../SAR_cap_array/test_adc_ahdl/schematic/verilog.vams,91|57): No connection module found:Need an input port of discrete discipline logic, and an output port
of continuous discipline voltage.

sample_out ), .vrefpcontp( vrefpcontp[11:0] ), .dout( dout[11:0] ) );

In the elaboration options I have tried connectrules module 'mixedsignal' and 'connrules_18V_basic'. Each of these modules declares an elect2logic, logic2elec, and bidir connect rule - so I do not understand why the elaborator is unable to work.

I can post the connect modules if necessary, but they are the ones that came with the kit - $LDV_DIR/tools/affirma_ams/etc/connect_lib Still will appreciate any input however. Thanks! #### DenisMark ##### Full Member level 6 verilog.vams I had same problem when I studied ams-simulation with ams-designer. I don't know correct solution till, but i did so. 1. Create lib, ex. "amsLib" 2. Create cellviews for e2l and l2e connect modules in the lib ("symbol" and "verilogams" views) 3. Create cellview for connect rules module in the lib ( "verilogams" view). Name it as 'mixedsignal' 4. Give link to 'mixedsignal' in elaborator Good luck horzon ### horzon Points: 2 Helpful Answer Positive Rating #### atamez ##### Newbie level 6 cadence ams tutorial Thanks for your input. I did find the connect library and was able to compile it. It was in$LDV_INST_DIR/tools/affirma_ams/etc.

My question now is in regards to compiled verilog-ams code. There are some standard digital cells that came with my kit, and I was using their cmos_sch views in spectre. During netlisting AMS created verilog.vams views for these cells.

Now during elaboration I'm getting errors (see original message), and it doesn't like the transistor instances. So, my question is, in verilog-ams what is the correct way to instantiate MOS devices?

#### DenisMark

##### Full Member level 6
verilog-ams library_binding

I don't remember. U can look for Cadence documentation (for ex. verilogamsref).

#### atamez

##### Newbie level 6

DenisMark said:
I don't remember. U can look for Cadence documentation (for ex. verilogamsref).

I've been wandering through the cadence documentation (cdsdoc) for a while, but just can't find exactly what I'm looking for. I've also been following the AMS tutorial with limited success. Thanks though for your reply.

#### DenisMark

##### Full Member level 6
ncelab e cuvncm

Try type "nchelp ncelab SPPBYN" in console for detailed help. (I try it, but it isn't work in LDV5.0).

### atamez

Points: 2

#### atamez

##### Newbie level 6
ams compile connect rule

DenisMark said:
Try type "nchelp ncelab SPPBYN" in console for detailed help. (I try it, but it isn't work in LDV5.0).

Now I think we're getting somewhere

[ 182 ] % -: nchelp ncelab SPPBYN
ncelab/SPPBYN =
Spectre and spice primitives may only have ports connected by order.

Ok, so in short if my MOS device has four ports (g, s, d, b) I need to create instantiations without the .g(x) .s .d(z) .b(/gnd!) convention. I will search for a netlisting or compilation option that describes this.

Thanks!

#### DenisMark

##### Full Member level 6
connect rules in verilog

I use IC5.1.41 & LDV5.0, part of netlist for primitives looks like
resistor #(.r(1K)) (* integer library_binding = "analogLib"; *) R0
( NETZ9, cds_globals.\gnd! );
I don't know where u can change netlister options (u have newer version i see). Verify CDF properties of instances from "cmos090" lib, may it helps u.

### atamez

Points: 2

#### datone520

##### Junior Member level 3
can you say clearly about the correct way to instantiate MOS devices??atamez??thanks

#### datone520

##### Junior Member level 3

atamez said:
So, my question is, in verilog-ams what is the correct way to instantiate MOS devices?