Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence Allegro, how to fix impedance mismatch

Status
Not open for further replies.

shemo

Advanced Member level 4
Full Member level 1
Joined
Apr 26, 2002
Messages
105
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,296
Visit site
Activity points
709
In constraint manager I set the value for impedance and make all nets close to certain tolerances. Then I it auto route and have bunch of impedance mismatch DRCs

1)I thought its constraint driven tool, so it should have routed within the tolerance of impedance I specified.

2)How to fix impedance mismatch. I try delay tuning, it didn't work. It just adds more delay.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top