Your PDK should come with electrical design rule manual, that should contain all that information.
If it's missing, well, maybe foundry did not care to provide that, or in that technology no one care to check the current densities for dynamic problems.
You can always schek with your foundry.
What technology node are you working with?
Cadence has several tools helping to verify and design for current density - EAD (Electrically Aware Design), VoltusFi (IE / EM analysis for transistor-level designs), Voltus (IR / EM for gate level), etc.
There are also other EDA vendors providing IR / EM analysis tools - you can mix and match, it's interoperable, with standard interfaces (like DSPF or SPEF files, etc.).
There are also smaller EDA vendors, that offer alternative, and often very good solutions for IR / EM analysis.
In simple cases, when you have one or few wires / metal lines and vias in your design, you can check manually or visually, for current density.
In most of the practical and commerical designs, though, the layouts are so complex that it is absoluely impossible to check IR / EM manually, and you need to use EDA tools for that.