Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cache and DSP - some questions

Status
Not open for further replies.

brmadhukar

Advanced Member level 3
Joined
Jun 21, 2002
Messages
839
Helped
42
Reputation
84
Reaction score
11
Trophy points
1,298
Location
India
Activity points
6,783
Cache

Hi,
I was until now using DSP with no cache support and so was novice in uC knid of programming. Now I am supposed to port the same into DSP with cache. The DSP in question is Blackfin with L1 and L2 memory. The question is can I move program from L2 to L1 using DMA in background while I am using L1 for program execution. I do not want use L1 as cache.
TIA
 

Hi,
If the L1 cache is segmented and if the instruction being executed is in L1 can the other (segment) part of cache (can be configured) be filled in by DMA.
BR
 

Hi,
Can anyone point where I can look for answers for the above questions.
TIA
brmadhukar
 

are there any general reference books for cache programming, non RTOS based designs, RTOS designs, principles which deal with optimization of code and speed.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top