[SOLVED] Butterfly interconnection between input and output in VHDL

[Farid Shamani]

Dear friends,

I want to make interconnections between arbitrary number of inputs and outputs. The method that i am thinking is to use one array as inputs and another array as outputs. Then, by using an arbiter, connect the output ports to the desired input ones.

This is the link to the picture that i exactly want to do:
https://obrazki.elektroda.pl/9529582900_1370962806.jpg

I do appreciate if you have something better in mind to be shared.


Thank you

 

[axcdd]

hi

why not just write simple function

function inverse ( DIN : std_logic_vector)
  return std_logic_vector is
  variable result : std_logic_vector(0 to DIN'length-1);
  begin
    for j in 0 to DIN'lenght-1 loop
      result(j):= DIN(DIN'length-1-j);
    end loop; 
  return result;
end function inverse;

and if u want just some of them pass there range argument

 

[Farid Shamani]

Dear AXCDD,

Thank you for your reply. Since i am not that much familiar with functions and procedures, Does it make any sense if the inputs and outputs bandwidth are 16 bits?

 

[axcdd]

hmmm if i understood correctly you want to reverse X 16 bits connections.
In this case function which i wrote need to be slidly modified.

1st. definition of an array like

  TYPE connections IS ARRAY(natural range <>) OF std_logic_vector(15 downto 0);

and then modified function:

function inverse_connections ( DIN : connections)
  return connections is
  variable result : connections(0 to DIN'length-1);
  begin
    for j in 0 to DIN'length-1 loop
      result(j):= DIN(DIN'length-1-j);
    end loop; 
  return result;
end function inverse_connections;

and if it's needed to inverse buses and bits in buses , you can call inverse function inside inverse_connections.

 

[Farid Shamani]

Thank you friend. However I am not good at functions, you gave me the clue to go for them..

 

[axcdd]

functions got 1 to n arguments and always 1 out (marked as return) --! everythink is similar to C#.
generally its good practise to add them to your packages then write them and use in same block.
so on this butterfly block is could look like this

---

Code VHDL - [expand]
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--------------------------------------------------------------------------------
--! @file edaboard.vhd
--! @brief 
--! @author 
--! @date 2013.06.12
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
--! PACKAGE DECLARATION                                                      !--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
PACKAGE MY_PACKAGE is
  
  TYPE connections IS ARRAY(natural range <>) OF std_logic_vector(15 downto 0);
  
  function inverse_connections ( DIN : connections)
  return connections;
 
END PACKAGE MY_PACKAGE;
 
PACKAGE body MY_PACKAGE is
 
--! inverse function
  function inverse_connections ( DIN : connections)
    return connections is
    variable result : connections(0 to DIN'length-1);
    begin
      for j in 0 to DIN'length-1 loop
        result(j):= DIN(DIN'length-1-j);
      end loop; 
    return result;
  end function inverse_connections;
 
end MY_PACKAGE;
 
-------------------------------------------------------------------------------------
--! BUTTERFLY ENTITY                                                              !--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.MY_PACKAGE.all;  --! delaration of your package
 
  entity BUTTERFLY is
    generic (
      ARRAY_WIDTH : natural := 32 --! Number of 2 BYTE I/O buses
    );
    port (
      DIN : in connections(0 to ARRAY_WIDTH-1); 
      DOUT : out connections(0 to ARRAY_WIDTH-1)
    );
  end entity BUTTERFLY;
  
  architecture BEHAVE of BUTTERFLY is
  begin
    DOUT <= inverse_connections(DIN);  
  end architecture BEHAVE;
 
-------------------------------------------------------------------------------------
--!  TESTBENCH                                                                    !--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.MY_PACKAGE.all;  --! delaration of your package
 
 
entity BUTTERFLY_TB is
  constant  ARRAY_WIDTH : natural := 16; -- Number of 2 BYTE I/O buses (lower for simpler tst)
end entity BUTTERFLY_TB;
  
architecture BEHAVE of BUTTERFLY_TB is
    
  component BUTTERFLY is
    generic (
      ARRAY_WIDTH : natural := 32 --! Number of 2 BYTE I/O buses
    );
    port (
      DIN : in connections(0 to ARRAY_WIDTH-1); 
      DOUT : out connections(0 to ARRAY_WIDTH-1)
    );
  end component BUTTERFLY;
    
  signal TEST_IN : connections(0 to ARRAY_WIDTH-1) := (X"0000", X"1111", X"2222", X"3333", X"4444", X"5555",
                                                         X"6666", X"7777", X"8888", X"9999", X"AAAA", X"BBBB",
                                                         X"CCCC", X"DDDD", X"EEEE", X"FFFF");
                                                         
  signal BUTTERFLY_OUT, LEFT_PICTURE, RIGHT_PICTURE : connections(0 to ARRAY_WIDTH-1);
    
begin
  --! using entity
  UUT: BUTTERFLY generic map (ARRAY_WIDTH) port map (TEST_IN, BUTTERFLY_OUT);
  --! or straight function 
  RIGHT_PICTURE <= inverse_connections(TEST_IN);
  --! left picture
  LEFT_PICTURE <=inverse_connections(TEST_IN(0 to 7))&TEST_IN(8 to ARRAY_WIDTH-1);
end architecture BEHAVE;

---

 

[Farid Shamani]

Ooohhhhh man it is working properly... I wish i could add you to my friend list. You really helped me.

Thank you