S.Nikhil
Member level 1
Can anyone tell me about the bus handling capability of Synopsys Design Compiler.
Actually my design module contains a port named as io_epd_md which is again declared on input side as a 16 bit bus {input [15:0} io_epd_md; and these 16 bits are connected with some buffers inside the logic.
Thus while performing insert_dft step during scan insertion, the tool says that it cannot find
io_epd_md [0]
.
.
io_epd_md [15] in the netlist.
Is there a way to tell dc to recognize these bus bits.
Actually my design module contains a port named as io_epd_md which is again declared on input side as a 16 bit bus {input [15:0} io_epd_md; and these 16 bits are connected with some buffers inside the logic.
Thus while performing insert_dft step during scan insertion, the tool says that it cannot find
io_epd_md [0]
.
.
io_epd_md [15] in the netlist.
Is there a way to tell dc to recognize these bus bits.