bulk contact for RFIC design

[estradasphere]

Hi,

I use BSIM3v3.3 MOS transistor models for RFIC design. BSIM 3v3.3 does not include a substrate network but just a drain-bulk capacitance which may be insufficient at high frequencies. I decided to use a grounded substrate contact surrounding the transistors
to reduce the substrate resistance. The distance between the transistor and the contact is about 0.2 um. This is the smallest distance which doesn't cause a DRC error.

Does someone have experience with the substrate effect, let's say up to 20 GHz? How critical would be the effect of the substrate resistance on the output matching characteristics of an amplifier, even if a bulk contact surround the transistor is used?

Thanks.

 

[cdrguy]

i think you can change the transistor model to include the substrate network when simulating in schematic.
for the post-layout simulation, i have no idea how to simulate its effect. the extracted view from Diva only contains the model of nch and pch, even not RF model.

 

[khouly]

about the models , typically the foundaries provide u with the RF models which include the substarte network
but this models for are limited for range of width and length , and for a layout shape

khouly

 

[yibinhsieh]

I think the only way you can do is try and error. Because subtrate network effect is diffucult. Another way is that try to find the model from Founday.

Yibin.