nand gate astable
Let me see if I understand this correctly:
We start with in1=5V and in2=0 ----->out=5V
The capacitor starts charging from 0 to 5 depending on the CR time constant, so we have a ramp up curve.
After a certain threshold, in2 is supposed to be equal to logic 1 and then the out=0. The capacitor starts to discharge down to the second threshold for the Schmidt Trigger, in2 is supposed to be equal to logic 0 then the output becomes logic one again and this goes on for ever.
If it so I undestand it. Now I have another :
What if the two inputs are short cicuited? Same topology only in1=in2? Then if we start from logic 0 then logic 0 is in the output - no charge of the capacitor.
Suppose now we add a second capacitor and a resistor in series in the output ( see diagram bellow). How does this works? Don't we have a stable logic 0 in the output no matter what? Do I miss something here?
The bjt is used to produce a signal to a transformer. My question is how we end there.